Exemplary embodiments of the present invention relate to a semiconductor device fabricating technology, and more particularly, to a method for fabricating a semiconductor device with a buried gate (BG).
Recently, research has actively been conducted for a buried gate (BG) in which a gate electrode is buried in a substrate in a semiconductor memory device, such as a DRAM, so that parasitic capacitance between a word line and a bit line can be significantly reduced. Such a buried gate is advantageous in that it can considerably increase the sensing margin of the semiconductor memory device.
FIGS. 1A to 1D are cross-sectional views illustrating the processes of a conventional method for fabricating a semiconductor device with a buried gate, and FIG. 2 is a graph showing breakdown voltage (BV) properties depending upon ways of forming a gate dielectric layer in the conventional method for fabricating a semiconductor device with a buried gate.
Referring to FIG. 1A, an active region 14 may be defined by forming an isolation layer 13 in a substrate 11, for example, a silicon substrate, through an STI (shallow trench isolation) process. The isolation layer 13 may be formed through a series of processes of forming a trench 12 for isolation through selectively etching the substrate 11, filling the trench 12 with a spin-on dielectric (SOD) layer, and annealing the filled spin-on dielectric layer.
The isolation layer 13 may be divided, depending upon a depth from the upper surface of the substrate 11, into an upper zone 13A which is well baked by the annealing process and a lower zone 13B which is less baked by the annealing process.
Referring to FIG. 1B, by selectively etching the substrate 11, recess patterns 15 may be formed in such a way as to extend simultaneously across the isolation layer 13 and the active regions 14. Hereafter, for the sake of convenience in explanation, the recess pattern 15 which is formed in the isolation layer 13 will be referred to as a first recess pattern 15A, and the recess pattern 15 which is formed in the active region 14 will be referred to as a second recess pattern 15B.
Referring to FIG. 1C, a gate dielectric layer 16 may be formed on the surface of the recess pattern 15 by conducting an oxidation process. At this time, due to the characteristics of the oxidation process, the gate dielectric layer 16 may not be formed on the surface of the first recess pattern 15A and may be formed only on the surface of the second recess pattern 15B. For reference, although the gate dielectric layer 16 may be formed also on the surface of the substrate 11 in the active region 14, illustration thereof will be omitted herein for the sake of convenience in explanation.
Referring to FIG. 1D, a buried gate may be formed through a series of processes of filling gate electrodes 17 partially in the recess patterns 15 and filling the remaining portions of the recess patterns 15 with a sealing layer 18.
In the conventional art, the gate dielectric layer 16 may be formed through 1 atm dry oxidation or low pressure radical oxidation which is implemented at a pressure lower than 1 atm. For reference, the 1 atm dry oxidation may represent an oxidation method which uses oxygen (O2) gas under 1 atm or the atmospheric pressure, and the low pressure radical oxidation may represent an oxidation method which uses oxygen radicals and hydrogen radicals produced under a low pressure less than several torrs using oxygen (O2) gas and hydrogen (H2) gas. The radicals may be produced at a low pressure less than 1 atm. In general, the low pressure radical oxidation has good oxidation capability, and it is known that generally the low pressure radical oxidation produces an oxide layer that is superior in quality to that of the 1 atm dry oxidation.
Referring to FIG. 2, in the case of forming the gate dielectric layer 16 through low pressure radical oxidation, it can be seen that electrical characteristics, in particular, breakdown voltage properties are superior to the case of the 1 atm dry oxidation. Accordingly, the gate dielectric layer 16 may be formed through the low pressure radical oxidation in consideration of quality.
However, when the gate dielectric layer 16 is formed through the low pressure radical oxidation by the conventional processes for forming the buried gate, the substrate may be warped more than in the case where the gate dielectric layer 16 is formed through the 1 atm dry oxidation. Furthermore, as the substrate 11 is warped, in overlay characteristics may be degraded in a photolithography process.
The reason why the substrate 11 is warped more when the gate dielectric layer 16 is formed through the low pressure radical oxidation may be explained as described below.
Referring to FIG. 1C, when conducting the process for forming the gate dielectric layer 16, outgassing of the impurities contained in the isolation layer 13, which includes the spin-on dielectric layer, may occur in the lower zone 13B of the isolation layer 13 which may be relatively less baked compared to the upper zone 13A of the isolation layer 13. In the case where the gate dielectric layer 16 is formed through the low pressure radical oxidation which is implemented at a pressure lower than the 1 atm dry oxidation, the outgassing of the impurities contained in the isolation layer 13 may occur to a greater extent. The outgassing of the impurities contained in the isolation layer 13 may cause volume shrinkage of the isolation layer 13. As the volume of the isolation layer 13 shrinks, a tensile stress in the isolation layer 13 may increase, and the substrate 11 may be warped (see FIGS. 9A and 9B, FIGS. 10A and 10B, and FIGS. 14A and 14B).